11:25 - 12:00  Paper 3

Challenges of debugging and testing high speed electrical serial buses

Dr Geoff Lawday, BCUC (Tektronix)

With the increasing trend where parallel buses are being replaced by high speed serial buses in a widening range of embedded applications, this is enabling significant improvements in data throughput moving from a  limiting 1Ghz parallel single ended signal rates to nearly 10Ghz through multi LVDS high speed serial signal paths, this huge improvement in data rates has raised the profile of signal integrity there are new test and measurement challenges that engineers need to consider in this high speed LVDS environment, In this paper we will look at key measurement issues.